Referring to FIG. 1, one or more dies 2 are formed in a conventional manner on a wafer 4, which is formed from a semiconductor material such as silicon. The dies 2 are integrated circuits or devices that have been formed, but have not been detached from the wafer 4. For clarity, only one row of dies 2 is shown, but will be understood that generally multiple rows of dies 2 are formed to substantially fill the wafer 4. During a wafer test procedure, conventional apparatus (not shown) electrically tests the dies 2. The testing apparatus includes probes that contact selected ones of the bond pads (not shown) of the dies 2.
A limitation associated with such a wafer test procedure is that each bond pad that will receive a signal from the testing apparatus often must be placed only along the sides 8 of the dies 2 in order to perform simultaneously testing of multiple dies 2. Because the dies 2 are placed relatively close together along their sides 6 to maximize the area of the wafer 4 occupied by the dies 2, the bond pads that are located along the adjacent sides 6 are often inaccessible to the probes of the testing apparatus, particularly when all of the dies 2 on the wafer 4 are tested simultaneously. That is, the probes of the testing apparatus can often only contact the accessible bond pads that are located along the other sides 8 of the dies 2. (The dies 2 are typically formed in the wafer 4 such that there is sufficient clearance for the test probes to access the sides 8 of each of the dies 2.) Requiring he bond pads that are used during the wafer test procedure to be located only along the sides 8 may cause inefficient and complex circuit layouts on and increase the areas of the dies 2.
Referring to FIG. 2, which shows a top view of a die 2 of FIG. 1, a known solution to this limitation is discussed. For clarity, the wafer 4 and the remaining dies 2 of FIG. 1 are omitted from FIG. 2. The die 2 includes accessible test pads 10 and accessible bond pads 14, which are located along accessible sides 8, and inaccessible pads 12, which are located along inaccessible sides 6. For clarity, FIG. 2 shows only two test pads 10a and 10b, two inaccessible bond pads 12a and 12b, and two accessible bond pads 14a and 14b, it being understood that the die 2 may include more or less of each of these pads. Each test pad 10 is electrically coupled to circuitry (not shown) that is coupled to a corresponding pad 12 and that is to receive a signal from the testing apparatus during a wafer test procedure. Thus, by physically accessing test pads 10, the testing apparatus can electrically access the circuitry that is coupled to the inaccessible pads 12. Once the test is complete, however, the pads 10 typically serve no further purpose.
A limitation of this known solution is that the length of the accessible sides 8 must be sufficient to accommodate the required number of the pads 14 and the test pads 10. Thus, the test pads 10 often increase the length of the sides 8, and thus often increase the area of the die 2.